//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// M8051W/EW Soft Core Top Level Module
// 
// $Log: m8051w.v,v $
// Revision 1.2  2002/03/12
// changed signal PC_CON to be the same with the VHDL
//
// Revision 1.1  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.1  2001/10/31
// First parsable verilog for EW
//
// Revision 1.1.1.1  2001/07/17
// Re-imported E-Warp from Farnham filesystem
//
// Revision 1.9  2000/10/24
// Multiplier rewritten to improve power consumption.
// Code changes for Leonardo (ECN01372).
// Code changes for formal verification tools (ECN01410).
// MOVX @Ri page address controllable from PORT2I if I/O ports ommitted (ECN01387).
//
// Revision 1.8  2000/05/17
// ECN01354: SFRRE qualifiication
//
// Revision 1.7  2000/02/21
// PROGDI to DPTR timing optimisation
//
// Revision 1.6  2000/02/20
// NINT0/1 sampling and condition zero ALU timing optimisation
//
// Revision 1.5  2000/02/15
// Renamed extended interrupts
//
// Revision 1.4  2000/02/05
// Name change repercussions
//
// Revision 1.3  2000/02/05
// Name change repercussions
//
// Revision 1.2  2000/02/05
// Renamed m8051ewarp as m8051ewarp
//
// Revision 1.1.2.1  2000/02/05
// Renamed m8051ewarp m8051ewarp
//
// Revision 1.6  1999/12/08
// Eliminate user instruction during state transition from interrupt service to
// debug state.
// RTL clean up of redundant declarations and sensitvity list entries.
//
// Revision 1.5  1999/11/30
// More debug changes.
//
// Revision 1.4  1999/11/18
// SFR read enable added, TRAP and DPTR fixes.
//
// Revision 1.3  1999/11/08
// VerilogXL syntax corrections
//
// Revision 1.2  1999/11/03
// Debug mode revisions.
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
// Revision 1.1  1999/10/22
// Initial revision
//
////////////////////////////////////////////////////////////////////////////////

`include "m8051w_cfg.v"

module m8051w (PORT0O, PORT1O, PORT2O, PORT3O, NPORT1E, NPORT2E, NPORT3E,
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
                   XRAMDO, PROGA, XRAMA, NPSEN, NPSWR, NXRAMR, NXRAMW, PROGA_EN,
                   XRAMA_EN, SOURCE_A, DESTIN_A, DESTIN_DO, NDESTIN_WE,
                   NSOURCE_RE, MXS_DO, MXS_A, NMXSWE, NMXSRE,
                   SFRWE, SFRRE, SFRSA, XINTR_ACK, NMI_ACK,
                   DebugAck, DebugRetract, DebugPFetch, DebugVector,
                   IDLE, PDOWN, NCCLKE, NPCLKE,
                   PORT0I, PORT1I, PORT2I, PORT3I, PROGDI, XRAMDI, SOURCE_DI,
                   MXS_DI, ESFRDI, XINTR_SRC, NMI, 
                   EXT2_OVERFLOW, EXT2_TCLK, EXT2_RCLK,
                   MWAIT, DebugReq, DebugStep,
                   SCLK, CCLK, PCLK, RESET, TRESET,
				   CANSEL); 
               
  //can sel from EOR in m3s009dy.v
  output		CANSEL;

  // Port Drivers

  output [7:0]  PORT0O;
  output [7:0]  PORT1O;
  output [7:0]  PORT2O;
  output [7:0]  PORT3O;

  // Port Driver Enables

  output [7:0]  NPORT1E;
  output [7:0]  NPORT2E;
  output [7:0]  NPORT3E;

  // Program Memory Interface

  output [`AddrSize-1:0] PROGA;
  output        NPSEN;
  output        NPSWR;
  output        PROGA_EN;

  // External Data RAM Interface

  output [`AddrSize-1:0] XRAMA;
  output [7:0]  XRAMDO;
  output        NXRAMR, NXRAMW;
  output        XRAMA_EN;

  // Dual port RAM interface

  output [7:0]  SOURCE_A;
  output [7:0]  DESTIN_A;
  output [7:0]  DESTIN_DO;
  output        NDESTIN_WE;
  output        NSOURCE_RE;

  // Memory extension stack interface
  output [7:0]  MXS_DO;
  output [6:0]  MXS_A;
  output        NMXSWE;
  output        NMXSRE;

  // External SFR Interface

  output [6:0]  SFRSA;
  output        SFRWE;
  output        SFRRE;

  // Extended Interrupt Acknowledges

  output [13:0] XINTR_ACK;
  output        NMI_ACK;

  // Debug OCI Interface

  output        DebugAck;
  output        DebugRetract;
  output        DebugPFetch;
  output        DebugVector;

  // External Controls

  output        IDLE;
  output        PDOWN;
  output        NPCLKE;
  output        NCCLKE;

  // Port Inputs

  input  [7:0]  PORT0I;
  input  [7:0]  PORT1I;
  input  [7:0]  PORT2I;
  input  [7:0]  PORT3I;

  // Program Memory Interface

  input  [7:0]  PROGDI;

  // External Data RAM Interface

  input  [7:0]  XRAMDI;

  // Dual port RAM Interface

  input  [7:0]  SOURCE_DI;

  // Memory extension stack interface

  input  [7:0]  MXS_DI;

  // External SFR Interface

  input  [7:0]  ESFRDI;

  // Extended Interrupt Sources

  input  [13:0] XINTR_SRC;
  input         NMI;

  // External Baudrate Generator inputs (optional)

  input         EXT2_OVERFLOW;
  input         EXT2_TCLK;
  input         EXT2_RCLK;

  // Slow memory synchronisation

  input         MWAIT;

  // Debug OCI Interface

  input         DebugReq;
  input         DebugStep;

  // Clocks and Resets

  input         SCLK, CCLK, PCLK;		
  input         RESET;
  input         TRESET;

  // interconnections between sub-modules

  // ALU

  wire [7:0]  REG_RESULT, ACC_RESULT, B_RESULT, DPTR_RESULT;
  wire [7:0]  OPERAND_A, OPERAND_B, MULDIV_A, MULDIV_B;
  wire        CARRY_RESULT, AUX_CARRY_RESULT, OVERFLOW_RESULT;
  wire        CONDITION_MET;
  wire [2:0]  BIT_ADDRESS;
  wire        MULDIV_OV;

  // Data Memory

  wire [7:0]  SOURCE_A, DESTIN_A, DESTIN_DO;
  wire [7:0]  INDIRECT_DATA;
  wire [6:0]  SFRSA;

  // SFRs

  wire [7:0]  ACC, B, PSW, STACK_POINTER, PCON;
  wire [7:0]  DPTR_SFR_DATA, PORTS_SFR_DATA, INTR_SFR_DATA;
  wire [7:0]  TIMER_SFR_DATA, UART_SFR_DATA;
  wire [7:0]  SFR_DATA;
  wire        SOURCE_IS_SFR, SFR_WRITE;
  wire [4:0]  SFR_WRITE_EN;
  wire        WRITE_PSW;

  // Program Address Registers

  wire [7:0]  SAVE_ADDR;
  wire        TRAP, WRPS;

  // Program Data and Opcode Decoding

  wire [7:0]  OPCODE, IMMEDIATE, IMMEDIATE_2;
  wire [18:0] ALU_CON;
  wire [5:0]  SWITCH_CON;
  wire [15:0] MEM_CON;
  wire [6:0]  SFR_CON;
  wire [16:0] PC_CON;
  wire [5:0]  STATE_CON;
  wire        IMM_CON, PORT_CON;
  wire        INTR_CON;

  // State Machine

  wire [2:0]  STATE;
  wire        LAST_CYC, INTERNAL_RESET, INTR_LCALL, NEXT_STATE_IDLE;
  wire        INTERNAL_WAIT;
  wire        NCCLKE, NPCLKE, PCLK_EN;
  wire        DebugHold, DebugNOP;
  
  // I/O Ports 

  wire [7:0]  PORT2O_I;
  wire [7:0]  PORT3O_I;
  wire [7:0]  NPORT3E_I;

  // Interrupt Controller 

  wire [13:0] INTR_ACKNOW;
  wire [13:0] INTR_SOURCE;
  wire [7:0]  INTR_VECTOR;
  wire        EXCEPTION;

  // Serial interface 

  wire        T1_OVERFLOW, T2_OVERFLOW, T2_TCLK, T2_RCLK;
  wire        INT2_OVERFLOW, INT2_TCLK, INT2_RCLK, TF2;
  wire        RXD, TXD, RXDNE, TXDNE;

  // Arithmetic Logic Unit 
 
  m3s003dy uALU  (.REG_RESULT(REG_RESULT), .ACC_RESULT(ACC_RESULT),
                  .B_RESULT(B_RESULT), .DPTR_RESULT(DPTR_RESULT), 
                  .CARRY_RESULT(CARRY_RESULT),
                  .AUX_CARRY_RESULT(AUX_CARRY_RESULT),
                  .OVERFLOW_RESULT(OVERFLOW_RESULT),
                  .CONDITION_MET(CONDITION_MET),
                  .OPERAND_A(OPERAND_A), .OPERAND_B(OPERAND_B),
                  .SAVE_ADDR(SAVE_ADDR), .PROGDI(PROGDI), .XRAMDI(XRAMDI),
                  .MULDIV_A(MULDIV_A), .MULDIV_B(MULDIV_B),
                  .MULDIV_OV(MULDIV_OV), .CARRY_FLAG(PSW[7]), .ALU_CON(ALU_CON),
                  .OPCODE(OPCODE[7:4]), .BIT_ADDRESS(BIT_ADDRESS));
  
  // Multiplier Divider 
 
  m3s005dy uMUL(.RESULT_A(MULDIV_A), .RESULT_B(MULDIV_B), .RESULT_OV(MULDIV_OV),
                .ACC(ACC), .B(B), .STATE(STATE), .INTERNAL_WAIT(INTERNAL_WAIT),
                .CCLK(CCLK), .MULNDIV(OPCODE[5]), .ENABLE(SFR_CON[2]));
  
  // ALU Operand Multiplexer 
 
  m3s004dy uAOM  (.OPERAND_A(OPERAND_A), .OPERAND_B(OPERAND_B),
                  .ACC(ACC), .PSW(PSW[7:6]),
                  .SOURCE_DI(SOURCE_DI), .SFR_DATA(SFR_DATA),
                  .IMMEDIATE(IMMEDIATE), .SWITCH_CON(SWITCH_CON),
                  .SOURCE_IS_SFR(SOURCE_IS_SFR));
  
  // Data Memory Interface 
 
  m3s006dy uDMI  (.SOURCE_A(SOURCE_A), .DESTIN_A(DESTIN_A),
                  .SFRSA(SFRSA), 
                  .INDIRECT_DATA(INDIRECT_DATA),
                  .STACK_POINTER(STACK_POINTER),
                  .NDESTIN_WE(NDESTIN_WE), .NSOURCE_RE(NSOURCE_RE),
                  .SFR_WRITE(SFR_WRITE),
                  .SOURCE_IS_SFR(SOURCE_IS_SFR),
                  .BIT_ADDRESS(BIT_ADDRESS), .PROGDI(PROGDI),
                  .OPCODE(OPCODE[2:0]), .PSW(PSW[4:3]), .SOURCE_DI(SOURCE_DI),
                  .MEM_CON(MEM_CON), .CONDITION_MET(CONDITION_MET),
                  .WRITE_PSW(WRITE_PSW),
                  .REG_RESULT(REG_RESULT), .SFR_WRITE_EN(SFR_WRITE_EN[3]),
                  .STATE(STATE), .LAST_CYC(LAST_CYC), .CCLK(CCLK),
                  .INTERNAL_WAIT(INTERNAL_WAIT),
                  .INTERNAL_RESET(INTERNAL_RESET));
  
  // SFR data multiplexer and SFR write strobe decoder 
 
  m3s007dy uSDM(.SFR_DATA(SFR_DATA), .SFR_WRITE_EN(SFR_WRITE_EN),
                .SOURCE_ADDR(SFRSA), .DESTIN_ADDR(DESTIN_A[6:0]), 
                .SFR_WRITE(SFR_WRITE), .STACK_POINTER(STACK_POINTER),
                .PSW(PSW), .ACC(ACC), .B(B), .PCON(PCON),
                .DPTR_SFR_DATA(DPTR_SFR_DATA), .PORTS_SFR_DATA(PORTS_SFR_DATA),
                .INTR_SFR_DATA(INTR_SFR_DATA), .TIMER_SFR_DATA(TIMER_SFR_DATA),
                .UART_SFR_DATA(UART_SFR_DATA),
                .ESFR_DATA(ESFRDI));
  
  // Core SFRs: ACC, B, and PSW. 
 
  m3s008dy uCSFR (.ACC(ACC), .B(B), .PSW(PSW), .WRITE_PSW(WRITE_PSW),
                  .REG_RESULT(REG_RESULT[7:1]), .ACC_RESULT(ACC_RESULT),
                  .B_RESULT(B_RESULT), .CARRY_RESULT(CARRY_RESULT),
                  .AUX_CARRY_RESULT(AUX_CARRY_RESULT),
                  .OVERFLOW_RESULT(OVERFLOW_RESULT),
                  .SFR_WRITE_EN(SFR_WRITE_EN[2:0]),
                  .SFR_CON(SFR_CON), .STATE(STATE), .LAST_CYC(LAST_CYC),
                  .INTERNAL_WAIT(INTERNAL_WAIT),
                  .CCLK(CCLK), .INT_RESET(INTERNAL_RESET));
  
  // Program Memory Interface 
 
  m3s009dy uPMI  (.PROGA(PROGA), .XRAMA(XRAMA), .MXS_DO(MXS_DO), .MXS_A(MXS_A),
                  .SAVE_ADDR(SAVE_ADDR), .DPTR_SFR_DATA(DPTR_SFR_DATA),
                  .NPSEN(NPSEN), 
                  .PROGA_EN(PROGA_EN), .NXRAMR(NXRAMR), .NXRAMW(NXRAMW),
                  .NMXSWE(NMXSWE), .NMXSRE(NMXSRE),
                  .NPSWR(NPSWR), .XRAMA_EN(XRAMA_EN), .TRAP(TRAP), .WRPS(WRPS),
                  .DebugVector(DebugVector),
                  .ACC(ACC), .PORT_2(PORT2O_I), .INDIRECT_DATA(INDIRECT_DATA),
                  .INTR_VECTOR(INTR_VECTOR), .IMMEDIATE(IMMEDIATE),
                  .IMMEDIATE_2(IMMEDIATE_2), .MXS_DI(MXS_DI),
                  .CONDITION_MET(CONDITION_MET), .EXCEPTION(EXCEPTION),
                  .INTR_LCALL(INTR_LCALL), .NEXT_STATE_IDLE(NEXT_STATE_IDLE),
                  .OPCODE(OPCODE[7:4]), .INTERNAL_RESET(INTERNAL_RESET),
                  .REG_RESULT(DPTR_RESULT), .DESTIN_ADDR(DESTIN_A[6:0]), 
                  .SFR_WRITE(SFR_WRITE), .SFR_S_ADDR(SFRSA),
                  .PC_CON(PC_CON), .STATE(STATE), .LAST_CYC(LAST_CYC),
                  .INTERNAL_WAIT(INTERNAL_WAIT), .DebugHold(DebugHold),
                  .CCLK(CCLK),
				  .CANSEL(CANSEL));
  
  // State Machine and Power Control Register 

  m3s010dy uSTM  (.STATE(STATE), .LAST_CYC(LAST_CYC),
                  .INTERNAL_WAIT(INTERNAL_WAIT),
                  .INTERNAL_RESET(INTERNAL_RESET),
                  .PCON(PCON), .NEXT_STATE_IDLE(NEXT_STATE_IDLE),
		  .DebugAck(DebugAck), .DebugHold(DebugHold),
		  .DebugNOP(DebugNOP), .DebugPFetch(DebugPFetch),
                  .DebugIUS(DebugIUS),
                  .NCCLKE(NCCLKE), .NPCLKE(NPCLKE), .PCLK_EN(PCLK_EN),
                  .PDOWN(PDOWN),
                  .SFR_WRITE_EN(SFR_WRITE_EN[4]), .REG_RESULT(REG_RESULT), 
                  .STATE_CON(STATE_CON),
                  .EXCEPTION(EXCEPTION), .MWAIT(MWAIT), .DebugReq(DebugReq),
		  .DebugStep(DebugStep), .TRAP(TRAP), .WRPS(WRPS),
		  .RESET(RESET), .TEST_RESET(TRESET),
                  .SCLK(SCLK), .CCLK(CCLK));
  
  // Program Data Registers for Opcode and Immediate Operands 

  m3s012dy uPDR  (.OPCODE(OPCODE), .IMMEDIATE(IMMEDIATE),
                  .IMMEDIATE_2(IMMEDIATE_2), .PROGDI(PROGDI), 
                  .EXCEPTION(EXCEPTION), .NEXT_STATE_IDLE(NEXT_STATE_IDLE),
                  .INTERNAL_RESET(INTERNAL_RESET), .STATE(STATE),
                  .PCLK_EN(PCLK_EN), .LAST_CYC(LAST_CYC), .IMM_CON(IMM_CON),
                  .INTERNAL_WAIT(INTERNAL_WAIT), .DebugNOP(DebugNOP),
                  .CCLK(CCLK), .PCLK(PCLK));
  
  // Opcode Decoder 

  m3s013dy uOPD  (.ALU_CON(ALU_CON), .SWITCH_CON(SWITCH_CON), .MEM_CON(MEM_CON),
                  .SFR_CON(SFR_CON), .PC_CON(PC_CON), .STATE_CON(STATE_CON),
                  .IMM_CON(IMM_CON), .PORT_CON(PORT_CON), .INTR_CON(INTR_CON),
                  .OPCODE(OPCODE));
  
  // I/O Ports

  `ifdef ExcludePorts
    assign PORTS_SFR_DATA = 8'h00;
    assign NPORT1E = 8'hff;
    assign NPORT2E = 8'hff;
    assign NPORT3E_I = 8'hff;
    assign PORT0O = 8'hff;
    assign PORT1O = 8'hff;
    assign PORT2O_I = PORT2I;
    assign PORT3O_I = 8'hff;
  `else
    m3s014dy uPORT (.PORTS_SFR_DATA(PORTS_SFR_DATA), .NPORT1E(NPORT1E),
                    .NPORT2E(NPORT2E), .NPORT3E(NPORT3E_I), .PORT0O(PORT0O),
                    .PORT1O(PORT1O), .PORT2O(PORT2O_I), .PORT3O(PORT3O_I),
                    .PORT0I(PORT0I), .PORT1I(PORT1I), .PORT2I(PORT2I),
                    .PORT3I(PORT3I), .SFRWE(SFRWE), .REG_RESULT(REG_RESULT),
		    .DESTIN_ADDR(DESTIN_A[6:0]), .SFRSA(SFRSA),
                    .PORT_CON(PORT_CON), .INTERNAL_RESET(INTERNAL_RESET),
                    .STATE(STATE[0]), .CCLK(CCLK));
  `endif
  
  // Interrupt Controller 

  m3s015dy uINTR (.INTR_SFR_DATA(INTR_SFR_DATA), .INTR_VECTOR(INTR_VECTOR),
                  .INTR_ACKNOW(INTR_ACKNOW[13:0]), .NMI_ACK(NMI_ACK),
                  .EXCEPTION(EXCEPTION), .INTR_LCALL(INTR_LCALL),
                  .DebugIUS(DebugIUS),
                  .INTR_SOURCE(INTR_SOURCE[13:0]), .NMI(NMI),
                  .REG_RESULT(REG_RESULT), .SFR_S_ADDR(SFRSA),
                  .DESTIN_ADDR(DESTIN_A[6:0]), .SFR_WRITE(SFR_WRITE),
                  .DebugHold(DebugHold),
                  .STATE(STATE[0]), .LAST_CYC(LAST_CYC), .INTR_RET(INTR_CON),
                  .PCLK_EN(PCLK_EN),
                  .INTERNAL_RESET(INTERNAL_RESET),
                  .INTERNAL_WAIT(INTERNAL_WAIT), .SCLK(SCLK), .CCLK(CCLK));
  
  // Timer Counters 

  `ifdef ExcludeTimers
    assign TIMER_SFR_DATA   = 8'h00;
    assign INTR_SOURCE[3:0] = XINTR_SRC[3:0];
    assign XINTR_ACK[3:0]   = INTR_ACKNOW[3:0];
    assign INTR_SOURCE[5]   = XINTR_SRC[5];
    assign XINTR_ACK[5]     = INTR_ACKNOW[5];
    assign T1_OVERFLOW      = 0;
    assign T2_OVERFLOW      = EXT2_OVERFLOW;
    assign T2_TCLK          = EXT2_TCLK;
    assign T2_RCLK          = EXT2_RCLK;
  `else
    m3s017dy uCNTR (.TIMER_SFR_DATA(TIMER_SFR_DATA), .IE0(INTR_SOURCE[0]),
                    .TF0(INTR_SOURCE[1]), .IE1(INTR_SOURCE[2]),
                    .TF1(INTR_SOURCE[3]), .TF2(TF2), .SFRSA(SFRSA),
                    .DESTIN_ADDR(DESTIN_A[6:0]), .SFRWE(SFR_WRITE), 
                    .REG_RESULT(REG_RESULT), .INTR_ACKNOW(INTR_ACKNOW[3:0]),
                    .PORT3I(PORT3I[5:2]), .PORT1I(PORT1I[1:0]), .RMW(PORT_CON),
		    .T1_OVERFLOW(T1_OVERFLOW), .T2_OVERFLOW(INT2_OVERFLOW),
                    .T2_TCLK(INT2_TCLK), .T2_RCLK(INT2_RCLK),
                    .INTERNAL_RESET(INTERNAL_RESET),
		    .PCLK_EN(PCLK_EN), .INTERNAL_WAIT(INTERNAL_WAIT),
                    .SCLK(SCLK), .CCLK(CCLK), .PCLK(PCLK));
    assign XINTR_ACK[3:0] = 4'h0;
  // Release unused Timer 2 resources
    `ifdef ExcludeTimer2
      assign T2_OVERFLOW    = EXT2_OVERFLOW;
      assign T2_TCLK        = EXT2_TCLK;
      assign T2_RCLK        = EXT2_RCLK;
      assign INTR_SOURCE[5] = XINTR_SRC[5];
      assign XINTR_ACK[5]   = INTR_ACKNOW[5];
    `else
      assign T2_OVERFLOW    = INT2_OVERFLOW;
      assign T2_TCLK        = INT2_TCLK;
      assign T2_RCLK        = INT2_RCLK;
      assign INTR_SOURCE[5] = TF2;
      assign XINTR_ACK[5]   = 0;
    `endif
  `endif
  

  // Serial Interface 

  `ifdef ExcludeUART
    assign UART_SFR_DATA = 8'h00;
    assign INTR_SOURCE[4] = XINTR_SRC[4];
    assign XINTR_ACK[4] = INTR_ACKNOW[4];
    assign TXD = 1'b1;
    assign RXD = 1'b1;
    assign TXDNE = 1'b1;
    assign RXDNE = 1'b1;
  `else
  // this definition changed for co-simulation purposes
  // the original one is .SFRWE(SFR_WRITE)
  // for the co-simulation we should put .SFR_WRITE(SFR_WRITE)
    m3s018dy uUART (.UART_SFR_DATA(UART_SFR_DATA), .RITI(INTR_SOURCE[4]),
                    .TXD(TXD), .RXD(RXD), .TXDNE(TXDNE), .RXDNE(RXDNE),
                    .SFR_S_ADDR(SFRSA), .DESTIN_ADDR(DESTIN_A[6:0]),
                    .PORT3I(PORT3I[0]), .SMOD(PCON[7]), .SFRWE(SFR_WRITE),
                    .REG_RESULT(REG_RESULT), .RMW(PORT_CON),
                    .T1_OVERFLOW(T1_OVERFLOW), .T2_OVERFLOW(T2_OVERFLOW),
                    .T2_TCLK(T2_TCLK), .T2_RCLK(T2_RCLK), 
                    .INTERNAL_RESET(INTERNAL_RESET), .PCLK_EN(PCLK_EN),
                    .SCLK(SCLK), .CCLK(CCLK), .PCLK(PCLK));
    assign XINTR_ACK[4] = 0;
  `endif
  
  // Assign extended interrupt channels to external world 
   
  `ifdef ExtraInterrupts
    assign INTR_SOURCE[13:6]  = XINTR_SRC[13:6];
    assign XINTR_ACK[13:6]    = INTR_ACKNOW[13:6];
  `else
    assign INTR_SOURCE[13:6]  = 9'b000000000;
    assign XINTR_ACK[13:6]    = 9'b000000000;
  `endif
  
  // External Pin Names for Internally-named Nets 
   
  assign XRAMDO             = ACC;
  assign IDLE               = PCON[0];
  assign DESTIN_DO          = REG_RESULT;
  assign SFRWE              = SFR_WRITE;
  assign SFRRE              = SOURCE_IS_SFR;
  assign PORT2O             = PORT2O_I;

  // Combine Serial Interface Outputs with Port 3 SFR outputs 
 
  assign PORT3O             = PORT3O_I & {6'b111111, TXD, RXD};
  assign NPORT3E            = NPORT3E_I & {6'b111111, TXDNE, RXDNE};
  assign DebugRetract       = NMI;

endmodule
